Silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) and complementary metal oxide semiconductors (CMOS) combined together and referred to as BiCMOS circuits and systems are one of the most promising and ready technologies for ultra-high frequency applications in the radio frequency (RF) and terahertz (THz) range. SiGe BiCMOS devices and circuits have been demonstrated for frequencies as high as 600 GHz, and are capable of integrating multiple speed and power devices in single integrated circuits. The frequency and power ranges are tuned for a particular application by altering the device geometry (smaller devices being for higher frequency applications) and the base epitaxy thickness (thinner epitaxy being for higher frequency applications).
However, the processing of SiGe BiCMOS comprises several steps that require additional consideration compared to conventional processes. Importantly, deposition steps require underlying surfaces to be pristine silicon surfaces to ensure devices and circuits function properly and material is not wasted. Additionally, the multiple surfaces and subsequent deposition steps need to be uniform and repeatable over large areas. To ensure a pristine surface typically requires a cleaning step immediately prior to the layer deposition, but in SiGe BiCMOS structures an oxide layer with a window down to the substrate is typically present whose geometry is a critical dimension for performance. Thus, designing a process flow ensuring retention of that geometric integrity is a crucial enabling technology for reliable SiGe BiCMOS production. A hard mask layer can be introduced, but the usual layers used for hard masking are typically not appropriate. For example, silicon nitride would be a candidate, but its high permittivity increases the SiGe HBT base-to-collector capacitance (Cbc) that directly reduces device frequency performance.